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淘豆网网友近日为您收集整理了关于单片机毕业设计 外文文献翻译中英文对照 89C52的内部结构分析的文档，希望对您的工作和学习有所帮助。以下是文档介绍：单片机毕业设计 外文文献翻译中英文对照 89C52的内部结构分析 1英文资料AT89C52 internal structure analysisDescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with8Kbytes of in-system programmable Flash memory. The device is manufactured usingAtmel’s high-density nonvolatile memory technology and patible with theindustry-standard 80C51 instruction set and pinout. The on-chip Flash allows theprogrammemory to be reprogrammed in-system or by a conventional nonvolatile memoryprogrammer. bining a versat(来源：淘豆网[/p-4291207.html])ile 8-bit CPU with in-system programmable Flash onamonolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides ahighly-flexible and cost-effective solution to many embedded control applications. TheAT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM,32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vectortwo-level interrupt architecture, a full duplex serial port(来源：淘豆网[/p-4291207.html]), on-chip oscillator,and clockcircuitry. In addition, the AT89S52 is designed with static logic for operationdown to zerofrequency and supports two software selectable power saving modes.The Idle Mode stopsthe CPU while allowing the RAM, timer/counters, serial port, andinterrupt system tocontinue functioning. The Power-down mode saves the RAM contentsbut freezes theoscillator, disabling all other chip functions until the next interruptor hardware re(来源：淘豆网[/p-4291207.html])set.Pin Supply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As anoutput port, each pin can sinkeight TTL inputs. When 1sare written to port 0 pins, the pins can be used ashighimpedanceinputs.Port 0 can also be configured to be the multiplexed loworderaddress/data bus during accesses to external program and data memory. In this mode, P02has internal pullups.Port 0 also receives the code bytes during Flash programming (来源：淘豆网[/p-4291207.html])andoutputs the code bytes during program verification.External pullups are required duringprogram verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers cansink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high by theinternal pullups and can be used as inputs. As inputs,Port 1 pins that are externally beingpulled low will source current (IIL) because of the internal (来源：淘豆网[/p-4291207.html])pullups. In addition, P1.0 andP1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and thetimer/counter 2 trigger input (P1.1/T2EX), respectively, asshown in the followingtable.Port 1 also receives the low-order address bytes duringFlash programming andverification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers cansink/source four TTL inputs.When 1s are written to Port 2 pin(来源：淘豆网[/p-4291207.html])s, they are pulled high bytheinternal pullups and can be used as inputs. As inputs,Port 2 pins that are externally beingpulled low will sourcecurrent (IIL) because of the internal pullups.Port 2 emits thehigh-order address byte during fetchesfrom external program memory and during accessestoexternal data memory that use 16-bit addresses (MOVX @DPTR). In this application,Port 2 uses strong internal pull-ups when emitting 1s. During accesses to extern(来源：淘豆网[/p-4291207.html])al datamemory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2Special Function Register. Port 2 also receives the high-order address bits and somecontrol signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers cansink/source four TTL inputs.When 1s are written to Port 3 pins, they are pulled high by theinternal pullups and can be used a(来源：淘豆网[/p-4291207.html])s inputs. As inputs,Port 3 pins that are externally beingpulled low will source current (IIL) because of the pullups.Port 3 also serves the functionsof various special features of the AT89S52, as shown in the following table.Port 3 alsoreceives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resetsthe device. This pin drives High for 96 oscillator p(来源：淘豆网[/p-4291207.html])eriods after the Watchdog times out.The3DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In thedefault state of bit DISRTO,the RESET HIGH out feature is enabled.ALE/PROGAddress Latch Enable (ALE) is an output pulse for latching the low byte of the addressduring accesses to external memory. This pin is also the program pulse input (PROG)during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 the(来源：淘豆网[/p-4291207.html])oscillator frequency and may be used for external timing or clocking purposes. Note,however, that one ALE pulse is skipped during each access to external data memory.Ifdesired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bitset, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin isweakly pulled high. Setting the ALE-disable bit has noeffect if the microcontroller is inexternal execution mode.PSENProgram Store Enable (PSEN) is the read strobe to externalprogram memory.When theAT89S52 is executing code from external program memory, PSEN is activated twice eachmachine cycle, except that two PSEN activations are skipped during each access toexternal data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device tofetch code from external program memory locations starting at 0000H up to FFFFH.Note,however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA shouldbe strapped to VCC for internal program executions.This pin also receives the 12-voltprogramming enable voltage (VPP) during Flash programming.XTAL1Input to the inverting oscillator amplifier and input to theinternal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Special Function RegistersA map of the on-chip memory area called the Special FunctionRegister (SFR) space isshown in Table 1.Note that not all of the addresses are occupied, and upied addressesmay not be implemented on the chip.Read accesses to these addresses will in generalreturn random data, and write accesses will have an indeterminate effect.User softwareshould not write 1s to these unlisted locations,since they may be used in future products to4invokenew features. In that case, the reset or inactive values of the new bits will always be0.Timer 2 Registers: Control and status bits are contained in registers T2CON (shown inTable 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H,RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bitauto-reload mode.Interrupt Registers: The individual interrupt enable bits are in the IE register. Twopriorities can be set for each ofthe six interrupt sources in the IP register.anizationMCS-51 devices have a separate address space for Program and Data Memory. Up to 64Kbytes each of external Program and Data Memory can be addressed.Program MemoryIf the EA pin is connected to GND, all program fetches are directed to externalmemory.On the AT89S52, if EA is connected to VCC, program fetches to addresses0000H through 1FFFH are directed to internal memory and fetches to addresses 2000Hthrough FFFFH are to external memory.Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy aparallel address space to the Special Function Registers. This means that the upper 128bytes have the same addresses as the SFR space but are physically separate from SFRspace. When an instruction accesses an internal location aboveaddress 7FH, the addressmode used in the instructionspecifies whether the CPU accesses the upper 128 bytes ofRAM or the SFR space. Instructions which use direct addressing access of the SFRspace.For example, the following direct addressing instruction accesses the SFR at location0A0H (which is P2). MOV 0A0H, #dataInstructions that use indirect addressing access the upper 128 bytes of RAM. For example,the following indirect addressing instruction, where R0 contains 0A0H, accesses the databyte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #dataNote that stack operations are examples of indirectaddressing, so the upper 128 bytes ofdata RAM are availableas stack space.Watchdog Timer(One-time Enabled with Reset-out)5The WDT is intended as a recovery method in situationswhere the CPU may be subjectedto software upsets. The WDT consists of a 13-bit counter and the Watchdog Timer Reset(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT,a user must write01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When theWDT is enabled, it will increment every machine cycle while the oscillator is running. TheWDT timeout period is dependent on the external clock frequency. There is no way todisable the WDT except through reset (either hardware reset or WDT overflow reset).When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.Using the WDTTo enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRSTregister (SFR location 0A6H).When the WDT is enabled, the user needs to service it bywriting 01EH and 0E1H to WDTRST to avoid a WDT overflow.The 13-bit counteroverflows when it reaches 8191(1FFFH), and this will reset the device. When the WDT isenabled, it will increment every machine cycle while the oscillator is running. This meansthe user must reset the WDT at least every 8191 machine cycles. To reset the WDT theuser must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. TheWDT counter cannot be read or written. When WDT overflows, it will generate an outputRESET pulse at the RST pin. The RESET pulse duration is 96xTOSC, whereTOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sectionsof code that will periodically be executed within the time required to prevent a WDT reset.WDT During Power-down and IdleIn Power-down mode the oscillator stops, which means the WDT also stops. While inPower-down mode, the user does not need to service the WDT. There are two methods ofexiting Power-down mode: by a hardware reset or via a level-activated external interruptwhich is enabled prior toentering Power-down mode. When Power-down is exited with hardware reset, servicingthe WDT should occur as it normally does whenever the AT89S52 is reset. ExitingPower-down with an interrupt is significantly different. The interrupt is held low longenough for the oscillator to stabilize. When the interrupt is brought high, the interrupt isserviced. To prevent the WDT from resetting the device while the interrupt pin is held low,the WDT is not started until the interrupt is pulled high. It is suggested that the WDT bereset during the interrupt service for the interrupt used to exit Power-down mode.To ensure6that the WDT does not overflow within a few states of exiting Power-down, it is best toreset the WDT just before entering Power-down mode. Before going into the IDLE mode,the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues tocount if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the defaultstate. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the usershould always set up a timer that will periodically exit IDLE, service the WDT, and reenterIDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode andresumes the count upon exit from IDLE.UARTThe UART in the AT89S52 operates the same way as the UART in the AT89C51 andAT89C52. For further information on the UART operation, refer to the ATMEL Web site(). From the home page, select ‘Products’,then ‘8051-ArchitectureFlash Microcontroller’, then‘Product Overview’.Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same wayas Timer 0 and Timer 1 in theAT89C51 and AT89C52. Forfurther information on the timers’ operation, refer to theATMEL Web site (). From the home page, select ‘Products’, then‘8051-Architecture Flash Microcontroller’, then ‘Product Overview’.Timer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter.The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2).Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baudrate generator. The modes are selected by bits in T2CON, as shown in Table 3. Timer 2consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register isincremented every machine cycle. Since a machine cycle consists of 12 oscillator periods,the count rate is 1/12 of the oscillator frequency.In the Counter function, the register is incremented in response to a 1-to-0 transition at itscorresponding external input pin, T2. In this function, the external input is sampled duringS5P2 of every machine cycle. When the samples show a high in one cycle and a low in thenext cycle, thecount is incremented. The new count value appears in the register during S3P1 of the cyclefollowing the one in which the transition was detected. Since two machine cycles (24oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is71/24 of the oscillator frequency.To ensure that a given level is sampled at least once beforeit changes, the level should be held for at leastone full machine cycle.Capture ModeIn the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0,Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON.This bitcan then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the sameoperation, but a 1- to-0 transition at external input T2EX also causes the current value inTH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, thetransition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, cangenerate an interrupt. The capture mode is illustrated in Figure 5.Auto-reload (Up or Down Counter)Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reloadmode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFRT2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default tocount up. When DCEN is set, Timer 2 can count up or down, depending on the value of theT2EX pin.Figure 6 shows Timer 2 automatically counting up when DCEN=0. In this mode,two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timerregisters to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values inTimer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at externalinput T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits cangenerate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up ordown,as shown in Figure 6. In this mode, the T2EX pin controls the direction of the count.A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and setthe TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to bereloaded into the timer registers,TH2 and TL2, respectively. A logic 0 at T2EX makesTimer 2 count down. The timer underflows when TH2 and TL2 equal the values stored inRCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloadedinto the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflowsand can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag aninterrupt.8中文翻译89C52的内部结构分析功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器,具有8K 在系统可编程Flash 存储器。使用Atmel 公司高密度非易失性存储器技术制造,与工业80C51 产品指令和引脚完全兼容。片上Flash允许程序存储器在系统可编程,亦适于常规编程器。在单芯片上,拥有灵巧的8 位CPU 和在系统可编程Flash,使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。AT89S52具有以下标准功能:8k字节Flash,256字节RAM,32 位I/O 口线,看门狗定时器,2 个数据指针,三个16 位定时器/计数器,一个6向量2级中断结构,全双工串行口,片内晶振及时钟电路。另外,AT89S52 可降至0Hz 静态逻辑操作,支持2种软件可选择节电模式。空闲模式下,CPU停止工作,允许RAM、定时器/计数器、串口、中断继续工作。掉电保护方式下,RAM内容被保存,振荡器被冻结,单片机一切工作停止,直到下一个中断或硬件复位为止。VCC : 电源GND: 地P0 口:P0口是一个8位漏极开路的双向I/O口。作为输出口,每位能驱动8个TTL逻辑电平。对P0端口写“1”时,引脚用作高阻抗输入。当访问外部程序和数据存储器时,P0口也被作为低8位地址/数据复用。在这种模式下,P0具有内部上拉电阻。在flash编程时,P0口也用来接收指令字节;在程序校验时,输出指令字节。程序校验时,需要外部上拉电阻。P1 口:P1 口是一个具有内部上拉电阻的8 位双向I/O 口,p1 输出缓冲器能驱动4 个TTL 逻辑电平。对P1 端口写“1”时,内部上拉电阻把端口拉高,此时可以作为输入口使用。作为输入使用时,被外部拉低的引脚由于内部电阻的原因,将输出电流(IIL)。此外,P1.0和P1.2分别作定时器/计数器2的外部计数输入(P1.0/T2)和时器/计数器2的触发输入(P1.1/T2EX),具体如下表所示。在flash编程和校验时,P1口接收低8位地址字节。P2 口:P2 口是一个具有内部上拉电阻的8 位双向I/O 口,P2 输出缓冲器能驱动4 个TTL 逻辑电平。对P2 端口写“1”时,内部上拉电阻把端口拉高,此时可9以作为输入口使用。作为输入使用时,被外部拉低的引脚由于内部电阻的原因,将输出电流(IIL)。在访问外部程序存储器或用16位地址读取外部数据存储器(例如执行MOVX @DPTR)时,P2 口送出高八位地址。在这种应用中,P2 口使用很强的内部上拉发送1。在使用8位地址(如MOVX @RI)访问外部数据存储器时,P2口输出P2锁存器的内容。在flash编程和校验时,P2口也接收高8位地址字节和一些控制信号。P3 口:P3 口是一个具有内部上拉电阻的8 位双向I/O 口,p2 输出缓冲器能驱动4 个TTL 逻辑电平。对P3 端口写“1”时,内部上拉电阻把端口拉高,此时可以作为输入口使用。作为输入使用时,被外部拉低的引脚由于内部电阻的原因,将输出电流(IIL)。P3口亦作为AT89S52特殊功能(第二功能)使用,如下表所示。在flash编程和校验时,P3口也接收一些控制信号。RST: 复位输入。晶振工作时,RST脚持续2 个机器周期高电平将使单片机复位。看门狗计时完成后,RST 脚输出96 个晶振周期的高电平。特殊寄存器AUXR(地址8EH)上的DISRTO位可以使此功能无效。DISRTO默认状态下,复位高电平有效。ALE/PROG:地址锁存控制信号(ALE)是访问外部程序存储器时,锁存低8 位地址的输出脉冲。在flash编程时,此引脚(PROG)也用作编程输入脉冲。在一般情况下,ALE 以晶振六分之一的固定频率输出脉冲,可用来作为外部定时器或时钟使用。然而,特别强调,在每次访问外部数据存储器时,ALE脉冲将会跳过。如果需要,通过将地址为8EH的SFR的第0位置“1”,ALE操作将无效。这一位置“1”,ALE 仅在执行MOVX 或MOVC指令时有效。否则,ALE 将被微弱拉高。这个ALE 使能标志位(地址为8EH的SFR的第0位)的设置对微控制器处于外部执行模式下无效。PSEN:外部程序存储器选通信号(PSEN)是外部程序存储器选通信号。当AT89S52从外部程序存储器执行外部代码时,PSEN在每个机器周期被激活两次,而在访问外部数据存储器时,PSEN将不被激活。EA/VPP:访问外部程序存储器控制信号。为使能从0000H 到FFFFH的外部程序存储器读取指令,EA必须接GND。为了执行内部程序指令,。在flash编程期间,EA也接收12伏VPP电压。XTAL1:振荡器反相放大器和内部时钟发生电路的输入端。XTAL2:振荡器反相放大器的输出端。特殊功能寄存器特殊功能寄存器(SFR)的地址空间映象如表1所示。并不是所有的地址都被定义了。片上没有定义的地址是不能用的。读这些地址,一般将得到一个随机数据;写入的数据将会无效。用户不应该给这些未定义的地址写入数据“1”。由于这10些寄存器在将来可能被赋予新的功能,复位后,这些位都为“0”。定时器2 寄存器:寄存器T2CON 和T2MOD 包含定时器2 的控制位和状态位,寄存器对RCAP2H和RCAP2L是定时器2的捕捉/自动重载寄存器。中断寄存器:各中断允许位在IE寄存器中,六个中断源的两个优先级也可在IE中设置。存储器结构MCS-51器件有单独的程序存储器和数据存储器。外部程序存储器和数据存储器都可以64K寻址。程序存储器:如果EA引脚接地,程序读取只从外部存储器开始。对于89S52,如果EA ,程序读写先从内部存储器(地址为0000H~1FFFH)开始,接着从外部寻址,寻址地址为:2000H~FFFFH。数据存储器:AT89S52 有256 字节片内数据存储器。高128 字节与特殊功能寄存器重叠。也就是说高128字节与特殊功能寄存器有相同的地址,而物理上是分开的。当一条指令访问高于7FH 的地址时,寻址方式决定CPU 访问高128 字节RAM还特殊功能寄存器空间。直接寻址方式访问特殊功能寄存器(SFR)。例如,下面的直接寻址指令访问0A0H(P2口)存储单元MOV 0A0H , #data使用间接寻址方式访问高128 字节RAM。例如,下面的间接寻址方式中,R0 内容为0A0H,访问的是地址0A0H的寄存器,而不是P2口(它的地址也是0A0H)。MOV @R0 , #data堆栈操作也是简介寻址方式。因此,高128字节数据RAM也可用于堆栈空间。看门狗定时器WDT是一种需要软件控制的复位方式。WDT 由13位计数器和特殊功能寄存器中的看门狗定时器复位存储器(WDTRST)构成。WDT 在默认情况下无法工作;为了激活WDT,户用必须往WDTRST 寄存器(地址:0A6H)中依次写入01EH 和0E1H。当WDT激活后,晶振工作,WDT在每个机器周期都会增加。WDT计时周期依赖于外部时钟频率。除了复位(硬件复位或WDT溢出复位),没有办法停止WDT工作。当WDT溢出,它将驱动RSR引脚一个高个电平输出。WDT的使用为了激活WDT,用户必须向WDTRST寄存器(地址为0A6H的SFR)依次写入0E1H和0E1H。当WDT激活后,用户必须向WDTRST写入01EH和0E1H喂狗来避免WDT溢出。当计数达到8191(1FFFH)时,13 位计数器将会溢出,这将会复位器件。晶振正常工作、WDT激活后,每一个机器周期WDT 都会增加。为了复位WDT,用户必须向WDTRST写入01EH 和0E1H(WDTRST 是只读寄存器)。WDT 计数器不能读或写。当WDT 计播放器加载中，请稍候...
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单片机毕业设计 外文文献翻译中英文对照 89C52的内部结构分析 1英文资料AT89C52 internal structure analysisDescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with8Kbytes of in-system programmable Flash memory. The device is manufactured usingAtmel’s high-density nonvolati...
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